www.iterrac.com IT4031F 100-ps wideband phase delay december 11, 2006 doc. 4093 rev 1.5 1 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 this is a production data sheet. see product statu s definitions on web site or catalog for product development stat us. description features device diagram the IT4031F is a rohs-6-compliant, ultra-wideband p hase delay fabricated using 1-um hbt gaas technology and is based on ecl topology to gua rantee high-speed operation. the high output voltage, excellent rise and fall time, and t he high eye diagram quality at data rates to 12.5 gb/s makes the IT4031F is suitable for timing adjus tment in data and clock distribution at very high speed. complex digital applications benefit fr om the IT4031F, including clock data recovery, edge detectors, nrz-to-rz converters, mux/demux, an d data restoration. the device features a single delay element that pro vides up to 100-ps delay. delay control can be either differential (using both vcp and vcm) or single-ended (vcm is the active control pad while vcp is shorted to vcref). the control voltage range for the delay input is from -2.2 v to -3.0 v whether the control is single-ended or differenti al. the device can delay nrz streams with data rates to 12.5 gb/s or a clock signal up to 10.7 ghz . both inputs and outputs are dc-coupled. the IT4031F uses scfl i/o levels and is designed so to allow for either single ended or differential data input. ultra wideband: up to 12.5 gb/s nrz delay adjustment to 100 ps 900 mvpp single-ended output jitter degradation rms: <1.5 ps output rise time (20% C 80 %):25 ps typical output fall time (20% C 80 %): 23 ps typical differential or single-ended i/o power consumption: 1.65 w output impedance: 300 ohms rohs-6 compliant 5x5-mm qfn (mo-220) package timing diagram
www.iterrac.com IT4031F 100-ps wideband phase delay december 11, 2006 doc. 4093 rev 1.5 2 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 this is a production data sheet. see product statu s definitions on web site or catalog for product development stat us. absolute maximum ratings recommended operating conditions stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v -0.45 dc input voltage (with dc-coupled input) v indc v -0.9 input voltage level, low level (single ended) v il v 0.0 input voltage level, high level (single ended) v ih v -2.2 -2.6 -3.0 delay control voltage vc v -5 power supply voltage v ee c 85 0 operating temperature range C die t a units max typ. min. parameters/conditions symbol electrical characteristics 1. electrical characteristics at ambient temperature. 2. in case of single- ended input, the unused pad must be tied to vindc. 3. in case of single- ended output, the unused pad must be terminated with 50 ohms to ground. 4. refer to timing diagram. c 150 -65 storage temperature tstg c 125 -15 operating temperature range C die ta v 0 -5.0 delay control voltage vc v 1.5 -1.5 input voltage level, low level vil v 1.5 -1.5 input voltage level, high level vih v 0 -5.5 power supply voltage vee units max. min. parameters/conditions symbol ps 300 output delay high-low transition (4) tdl ps 300 output delay low-high transition (4) tdh ps 23 output fall time (20% C 80%) tf ps 25 output rise time (20% C 80%) tr v 1.0 0.9 0.8 data output voltage amplidude (3) vout v -0.45 dc input voltage (with dc-coupled input) (2) vindc v -0.9 input voltage level, low level (single ended) vil v 0.0 input voltage level, high level (single ended) vih v -5.25 -5.00 -4.5 power supply voltage vee units max. typ. min. parameters symbol
www.iterrac.com IT4031F 100-ps wideband phase delay december 11, 2006 doc. 4093 rev 1.5 3 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 this is a production data sheet. see product statu s definitions on web site or catalog for product development stat us. electrical characteristics (cont.) w 1.65 power dissipation p d ma 330 power supply current i ee ps 1.5 jitter rms degradation j drms ghz 10.7 maximum clock frequency f max ps 100 output phase delay adjustment (4) t adj units max. typ. min. parameters symbol eye diagram performance evaluation board measurement vee: -5.0 v input data rate: 10.7 gb/s single-ended data input: +/-450 mvpp control voltage: vcp = vcref, vcm =- 2.2 v evaluation board measurement vee: -5.0 v input data rate: 10.7 gb/s single-ended data input: +/-450 mvpp control voltage: vcp = vcref, vcm = -3.0 v evaluation board measurement vee: -5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcp = vcref, vcm =- 2.2 v evaluation board measurement vee: -5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcp = vcref, vcm = -3.0 v 2 2 thru meas drms j j j - =
www.iterrac.com IT4031F 100-ps wideband phase delay december 11, 2006 doc. 4093 rev 1.5 4 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 this is a production data sheet. see product statu s definitions on web site or catalog for product development stat us. recommended operational setup eye diagram performance (cont.) evaluation board measurement vee: -5.0 v input data rate: 12.5 gb/s single-ended data input: +/-450 mvpp control voltage: vcp = vcref, vcm = -2.2 to -3.0 v (accumulating) evaluation board measurement vee: -5.0 v input clk frequency: 12.5 ghz single-ended clk input: +/-450 mvpp control voltage: vcp = vcref, vcm = -2.2 v IT4031F
www.iterrac.com IT4031F 100-ps wideband phase delay december 11, 2006 doc. 4093 rev 1.5 5 iterra communications 2400 geng road, ste. 100, palo alto, ca 94303 phone (650) 424-1937, fax (650) 424-1938 this is a production data sheet. see product statu s definitions on web site or catalog for product development stat us. f package drawing, pinouts, and marking pinouts p1: vee p11: vee p2: din p12: dout p3: n/c p13: n/c p4: din/ p14: dout/ p5: vee p15: vee p6: n/c p16: vee p7: vcm p17: n/c p8: vcp p18: n/c p9: vcref p19: n/c p10: vee p20: n/c notes: dimensions in inches (mm) tolerances are 0.0039 in. (0.100 mm) package drawing encompasses jedec mo-220 version vhhc-2 see iterra application note 10 for recommended pad layout. rohs parts are backward compatible if application note pad layout is followed. lead frame material is copper alloy mold compound is ul94v0 compliant lead finish is nipdau marking information iterra mmmmfa xxnnnn llyyww where mmmm = part number f = package type a = temp. range xx = wafer lot nnnn=ser. no. llyyww = mfg d/c
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